Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs

Keyphrases

• Power Efficiency 100%
• Variable Latency 100%
• Timing Margin 100%
• Time Variability 75%
• Power Consumption 50%
• Genetic Algorithm 25%
• Power Issue 25%
• Circuit Performance 25%
• Design Requirements 25%
• Circuit Area 25%
• Aging Effect 25%
• Design Considerations 25%
• Power Efficient 25%
• Leakage Power 25%
• Process Variation Effect 25%
• Design Paradigms 25%
• Design Circuit 25%
• Gate Delay 25%
• Dynamic Power Reduction 25%

Computer Science

• Power Consumption 100%
• Power Efficiency 100%
• Experimental Result 50%
• Power Efficient 50%
• Process Variation 50%
• Design Consideration 50%
• Paradigm Design 50%
• Dynamic Power 50%
• Design Constraint 50%
• Genetic Algorithm 50%