Evaluation of A D-band divide-by-3 injection-locked frequency divider in 65 nm CMOS process

Yen Liang Yeh, Yu Cheng Liu, Hong Yeh Chang, Kevin Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, a D-band divider-by-3 injectionlocked frequency divider is presented using 65 CMOS process. By using the technique of the second harmonic boosting, the input sensitivity and locking range can be enhanced in the millimeter-wave band without additional dc power consumption. As the input frequency is 134.6 GHz with a RF power of -8.5 dBm, the measured locking range is 0.4 GHz without varactor tuning, and the output power is high than -18 dBm. The core dc power consumption is 2.3 mW.

Original languageEnglish
Title of host publication2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages184-186
Number of pages3
ISBN (Electronic)9781467377942
DOIs
StatePublished - 8 Jan 2016
EventIEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Sendai, Japan
Duration: 26 Aug 201528 Aug 2015

Publication series

Name2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings

Conference

ConferenceIEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015
Country/TerritoryJapan
CitySendai
Period26/08/1528/08/15

Keywords

  • CMOS
  • D-band
  • Frequency divider
  • Millimeter-wave (MMW)
  • Voltage-controlled oscillator

Fingerprint

Dive into the research topics of 'Evaluation of A D-band divide-by-3 injection-locked frequency divider in 65 nm CMOS process'. Together they form a unique fingerprint.

Cite this