Evaluation driven layout synthesis

A. C.H. Wu, D. D. Gajski, G. D. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The authors describe a layout synthesis system for layout generation from generalized register-transfer schematics. This system uses the SLAM partitioner and the ICDB component server. The system is performed in a completely top-down manner which generates the layout by considering the component layout style, floorplan, and critical paths simultaneously. This improves the overall area utilization and minimizes the critical wire lengths, which in turn yields better performance.

Original languageEnglish
Title of host publication1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages167-171
Number of pages5
ISBN (Electronic)078030036X, 9780780300361
DOIs
StatePublished - 1991
Event1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991 - Taipei, Taiwan
Duration: 22 May 199124 May 1991

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991
Country/TerritoryTaiwan
CityTaipei
Period22/05/9124/05/91

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