Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs

Tai Ying Jiang, Jing Yang Jou, Chien Nan Jimmy Liu

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations

Abstract

Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.

Original languageEnglish
Article number1465927
Pages (from-to)5682-5685
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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