TY - JOUR
T1 - Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs
AU - Jiang, Tai Ying
AU - Jou, Jing Yang
AU - Liu, Chien Nan Jimmy
PY - 2005
Y1 - 2005
N2 - Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.
AB - Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.
UR - http://www.scopus.com/inward/record.url?scp=47949102761&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465927
DO - 10.1109/ISCAS.2005.1465927
M3 - 會議論文
AN - SCOPUS:47949102761
SN - 0271-4310
SP - 5682
EP - 5685
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1465927
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -