Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs

Yu Jen Huang, Yun Chao You, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

IEEE 1500 test wrapper wraps logic cores in system-on-chips (SOCs) for the core test and isolation. On the other hand, random access memory (RAM) cores are typically tested using the built-in self-test (BIST) circuit instead of using the IEEE 1500 test wrapper. But, RAM cores are usually connected to logic cores. This paper proposes an enhanced IEEE 1500 test wrapper to support the testing of the RAM core attached to the test wrapper. Furthermore, the memories attached to the enhanced IEEE 1500 test wrappers can be tested in parallel. Simulation results show that the additional area cost for upgrading the IEEE 1500 test wrapper to an enhanced one is only about 0.88% for a 102464-bit RAM.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2010
Pages236-240
Number of pages5
DOIs
StatePublished - 2010
Event23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States
Duration: 27 Sep 201029 Sep 2010

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference23rd IEEE International SOC Conference, SOCC 2010
Country/TerritoryUnited States
CityLas Vegas, NV
Period27/09/1029/09/10

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