Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2FETs for SoC Scaling

Vita Pi Ho Hu, Cheng Wei Su, Yen Wei Lee, Tun Yi Ho, Chao Ching Cheng, Tzu Chiang Chen, Terry Yi Tse Hung, Jin Fu Li, Yu Guang Chen, Lain Jong Li

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

In this article, we propose an energy-efficient monolithic 3-D (M3D) three-Tier SRAM cell with back-end-of-The-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-Technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-Tier BG SRAM cell design, the proposed monolithic three-Tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy-and area-efficient three-Tier BG SRAM cell enables intelligent functionalities for the area-and energy-constrained edge computing devices.

Original languageEnglish
Article number9184285
Pages (from-to)4216-4221
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume67
Issue number10
DOIs
StatePublished - Oct 2020

Keywords

  • 2-D material
  • SRAM
  • area efficiency
  • back-end-of-The-line (BEOL)
  • energy efficiency
  • monolithic 3-D (M3D) integration

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