Enabling the Duo-phase Data Management to Realize Longevity Bit-alterable Flash Memory

Tseng Yi Chen, Shao Hung Chi, Ming Chang Yang, Ting Ying Chien

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


Bit-alterable flash memory is a cutting-edge technology that enables a novel operation, called page-level erase operation, to erase a flash page within a block arbitrarily. Though the page-level erase operation can ease the overhead of the live-page copying during a garbage collection process, it also introduces a new wear-leveling problem. In such the problem, flash pages within the same block will receive different program/erase (P/E) cycles during runtime. Some specific pages storing hot data will be worn out soon; therefore, the lifespan of the bit-alterable flash memory will be short due to the uneven worn out of flash pages. Consequently, it becomes a critical issue with the bit-alterable flash memory, and the state-of-art wear-leveling designs cannot resolve this problem. For tackling the problem, this study presents a duo-phase data management scheme considering the page-level wear-leveling issue. The duo-phase mechanism simultaneously cares about page- and block-level wear-leveling issues. On the page-level wear-leveling problem, the duo-phase scheme identifies hot flash pages via the few bits and softly restricts the hot flash page to store hot data. On the other hand, our proposed mechanism also figures out the solution to minimize the number of copied live pages for the block-level wear-leveling issue.

Original languageEnglish
JournalIEEE Transactions on Computers
StateAccepted/In press - 2021


  • Ash
  • Bit-alterable flash
  • endurance
  • garbage collection
  • Logic gates
  • Memory architecture
  • Memory management
  • page-level wear-leveling
  • Programming
  • Regulators
  • Three-dimensional displays


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