Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

Tseng Yi Chen, Yuan Hao Chang, Chien Chung Ho, Shuo Han Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

24 Scopus citations

Abstract

3D NAND has been proposed to provide a large capacity storage with low-cost consideration due to its high density memory architecture. However, 3D NAND needs to consume enormous time for garbage collection because of live-page copying overhead and long block erase time. To alleviate the impact of live-page copying on the performance of 3D NAND, a sub-block erase design has been designed. With sub-block erase design, this paper proposes a performance booster strategy to extremely boost the performance of garbage collection. As experimental results shows, the proposed strategy has a significant improvement on the average response time.

Original languageEnglish
Title of host publicationProceedings of the 53rd Annual Design Automation Conference, DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450342360
DOIs
StatePublished - 5 Jun 2016
Event53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States
Duration: 5 Jun 20169 Jun 2016

Publication series

NameProceedings - Design Automation Conference
Volume05-09-June-2016
ISSN (Print)0738-100X

Conference

Conference53rd Annual ACM IEEE Design Automation Conference, DAC 2016
Country/TerritoryUnited States
CityAustin
Period5/06/169/06/16

Keywords

  • FTL
  • Garbage collection
  • NAND flash
  • Sub-block erased

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