Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms

Yu Guang Chen, Yiyu Shi, Kuan Yu Lai, Geng Hui, Shih Chieh Chang

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations

Abstract

Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal registers, it is imperative to minimize the total retention storage size. The current industry practice only replace all registers with single-bit retention ones, which significantly limits the design freedom and results in excessive area and power overhead. Towards this, for the first time in literature, we propose the concept of multi-bit retention register, with which only selected registers need to be replaced. It can significantly reduce the number of bits that need to be stored and thus the area and leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode and the retention storage area by 66.03%, compared with the single-bit retention register based design.

Original languageEnglish
Article number6386628
Pages (from-to)309-316
Number of pages8
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
StatePublished - 2012
Event2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States
Duration: 5 Nov 20128 Nov 2012

Keywords

  • Low power
  • power gating
  • retention register

Fingerprint

Dive into the research topics of 'Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms'. Together they form a unique fingerprint.

Cite this