Efficient implementation of interpolation technique for symbol timing recovery in DVB-T receiver design

This study considers a non-synchronized sampling scheme for symbol timing recovery in DVBT Transceiver design. The received signal is performed by a fixed sampling clock; the samples are not synchronized to the incoming data symbols. Timing adjustment is done after sampling using interpolation. The Lagrange interpolation for timing adjustment can be implemented FIR filter having changeable coefficients. This interpolation filter can be efficiently implemented using the Farrow structure. Take the advantage of symmetry property, this paper presents a low power/low-cost (0.64 mm² and 54.9mW) Farrow structure for cubic interpolation, where the standard cells in TSMC. 18um digital CMOS process were employed. Comparing the conventional structure, the developed structure achieves 36.8% lower power consumption and 24.3% low area cost than the conventional one. An efficient implementation of Farrow Structure for quintic interpolation is also presented.