Efficient hardware implementation of pipelined divider with a small lookup table

The design of fast dividers is an important issue in high speed computing because division account for a significant fraction of the total arithmetic operation. Taylor series expansion is a well-known multiplicative scheme for high-performance division implementation. This study presents a simple architecture that implements a pipelined divider including the first 6 terms of the Taylor series expansion for approximation. Results show that the developed pipelined divider further reduces the size of lookup table from 208B to 32B for single precision with a latency of 8.90ns, and from 56KB to 1.28KB for double precision with 11.46ns, where the circuit is synthesized with TSMC 0.18μm digital CMOS standard cell library. The overall area is improved from 264,924μm² to 238,494μm² for single precision, and from 21,422,752μm² to 1,041,319μm² for double precision. The significant area reduction for double precision is achieved at the cost of increasing the latency from 9.46ns to 11.46ns.