Efficient functional coverage test for HDL descriptions at RTL

Until now, simulation is still the primary approach for the functional verification of RTL circuit descriptions written in HDL. The FSM coverage test can find all bugs in a FSM design. However, it is impractical for large designs because of the state explosion problem. In this paper, we modify the higher level FSM models used in other applications to replace the FSM model in the FSM coverage test. The STGs can be significantly reduced in this model so that the complexity of the test becomes acceptable even for large designs. This model can be easily extracted from the original HDL code automatically with little computation overhead. The experimental results show that it is indeed a promising functional test for FSMs.