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Efficient coverage analysis metric for HDL design validation
C. N. Liu
, J. Y. Jou
Department of Electrical Engineering
Research output
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Contribution to journal
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Article
›
peer-review
9
Scopus citations
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Dive into the research topics of 'Efficient coverage analysis metric for HDL design validation'. Together they form a unique fingerprint.
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Keyphrases
Finite State Machine Models
100%
Language Design
100%
Hardware Description Language
100%
Design Validation
100%
Coverage Analysis
100%
Efficient Coverage
100%
Finite State Machine
40%
Coverage Test
40%
Coverage Metrics
20%
Functional Coverage
20%
Test Pattern
20%
State Transition Graph
20%
Design Errors
20%
Language Codes
20%
Functional Verification
20%
Simulation Approach
20%
Implementation Results
20%
Circuit Description
20%
Computation Overhead
20%
Register Transfer Level
20%
State Explosion Problem
20%
Computer Science
Finite-State Machine
100%
Design Validation
100%
Hardware Description Languages
100%
State Machine Model
71%
Coverage Test
28%
Simulation Approach
14%
State Transition
14%
Functional Verification
14%
Register-Transfer Level
14%
Transition Graph
14%
Engineering
Metrics
100%
Finite-State Machine
100%
Major Problem
14%
State Transition
14%