Efficient block-level connectivity verification algorithms for embedded memories

Keyphrases

• Verification Algorithm 100%
• Embedded Memory 100%
• Memory Block 100%
• Block Level 100%
• Large Memory 60%
• Evaluation Approach 40%
• Symbolic Trajectory Evaluation 40%
• Single System 20%
• Write Operation 20%
• Output Port 20%
• Verification Scheme 20%
• Verification Time 20%
• Reducing Power 20%
• Multiple Memories 20%
• Interports 20%
• Data Width 20%
• Address Data 20%
• Circuit Verification 20%
• Reduced Delay 20%
• Individual Memory 20%

Computer Science

• Evaluation Approach 100%
• embedded memory 100%
• Connectivity Verification 100%
• Write Operation 50%
• Memory Multiple 50%