Dynamic frequency tracking and phase error compensation clock de-skew buffer

K. H. Cheng, K. W. Hong, Y. L. Lo, C. L. Wu, C. H. Lee

Research output: Contribution to journalArticlepeer-review

Abstract

Proposed is a dynamic frequency tracking and phase error compensation clock de-skew buffer (CDSB) to reduce the clock skew between the input and output clocks of a chip. The proposed CDSB tracks the dynamic frequency in two clock cycles. Also, the CDSB utilises a fine tune circuit which is based on a cyclic rotation algorithm to compensate for the dynamic phase error. Measured results show that the operating frequencies of the CDSB are from 200 to 450MHz. Also, the CDSB tracks the dynamic frequency in two clock cycles. The power consumption, RMS jitter, and peak-to-peak jitter of the CDSB are 9.71mW, 2.7 ps, and 31.3 ps at 450MHz.

Original languageEnglish
Pages (from-to)1653-1655
Number of pages3
JournalElectronics Letters
Volume46
Issue number25
DOIs
StatePublished - 9 Dec 2010

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