DRC Violation Prediction After Global Route Through Convolutional Neural Network

Wei Tse Hung, Yu Guang Chen, Jhen Gang Lin, Yun Wei Yang, Cheng Hong Tsai, Mango Chia Tso Chao

Research output: Contribution to journalArticlepeer-review

Abstract

Design rule checking (DRC) violation (DRV) prediction with early stage design information can help to reduce the iterations of design procedure and can speed up the physical-design closure. It is known that accurately predicting detailed routing-level DRV with information obtained at global route (GR) stage can significantly speed up the design closure. However, without sufficient prediction accuracy, the result may lead to suboptimal design or even longer design time. Therefore, in this article, we propose two machine-learning frameworks to predict the detailed routing-level DRV map of a given design. The first framework is based on the congestion report obtained at global routing stage, and the second framework considers both the placement information and the congestion report of global routing. We then compare the runtime and accuracy of the two models. The proposed frameworks utilize convolutional neural network as the core technique to train these prediction models. The training dataset is collected from 15 industrial designs using a leading commercial automatic placement and routing (APR) tool, and the total number of collected training samples exceeds 26M. A specialized under-sampling technique is also proposed to select important training samples for learning, compensate for the inaccuracy misled by a highly imbalanced training dataset, and speed up the entire training process. The experimental results demonstrate that our both models can result in not only a significantly higher accuracy than previous related works, but also a DRV map visually matching the actual ones closely. The average runtime of using our learned model from the first framework to generate a DRV map is only 3% of global routing, and the prediction accuracy of our learned model from the second framework can improve 7.6% compared to the one from the first framework. Our proposed framework can be viewed as a simple add-on tool to a current commercial placement and global router that can efficiently and effectively generate a more realistic DRV map without really applying detailed routing.

Original languageEnglish
Pages (from-to)1425-1438
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume31
Issue number9
DOIs
StatePublished - 1 Sep 2023

Keywords

  • Design rule checking (DRC)
  • neural networks
  • physical design (EDA)
  • physical verification
  • supervised learning by classification

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