Distributed fault simulation for sequential circuits by pattern partitioning

Wen Ching Wu; Chung Len Lee; Jwu E. Chen; Won Yih Lin

Distributed fault simulation for sequential circuits by pattern partitioning

Wen Ching Wu, Chung Len Lee, Jwu E. Chen, Won Yih Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we target the pattern partitioning on the distributed fault simulation because the number of patterns can be reduced by a factor of n, the number of machines, and the faults detected by any machine can be dropped through the communication of the network.

Original language	English
Title of host publication	Proceedings of the European Design and Test Conference
Editors	Anon
Publisher	Publ by IEEE
Pages	661
Number of pages	1
ISBN (Print)	0818654112
State	Published - 1994
Event	Proceedings of the European Design and Test Conference - Paris, Fr Duration: 28 Feb 1994 → 3 Mar 1994

Publication series

Name	Proceedings of the European Design and Test Conference

Conference

Conference	Proceedings of the European Design and Test Conference
City	Paris, Fr
Period	28/02/94 → 3/03/94

Cite this

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title = "Distributed fault simulation for sequential circuits by pattern partitioning",

abstract = "In this paper, we target the pattern partitioning on the distributed fault simulation because the number of patterns can be reduced by a factor of n, the number of machines, and the faults detected by any machine can be dropped through the communication of the network.",

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Distributed fault simulation for sequential circuits by pattern partitioning. / Wu, Wen Ching; Lee, Chung Len; Chen, Jwu E. et al.
Proceedings of the European Design and Test Conference. ed. / Anon. Publ by IEEE, 1994. p. 661 (Proceedings of the European Design and Test Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Chung Len

AU - Chen, Jwu E.

AU - Lin, Won Yih

PY - 1994

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M3 - 會議論文篇章

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SN - 0818654112

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BT - Proceedings of the European Design and Test Conference

A2 - Anon, null

PB - Publ by IEEE

T2 - Proceedings of the European Design and Test Conference

Y2 - 28 February 1994 through 3 March 1994

ER -

Distributed fault simulation for sequential circuits by pattern partitioning

Abstract

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