DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs

Ze Wei Pan; Jin Fu Li

doi:10.1109/ITC50671.2022.00058

DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs

Ze Wei Pan, Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is one promising nonvolatile memory. In this paper, a design-for-testability (DFT)-enhanced test scheme is proposed to enhance the test quality of STT-MRAMs by adaptively adjusting the read current of the read test operations using a read current-adjustable DFT (RCA-DFT) circuit. A march test, March-MT, is proposed as well. Together with RCA-DFT, March-MT requires 11N test complexity to achieve about 7.26 times of total test quality improvement in comparison with a March-6N test algorithm with fixed read current for a STT-MRAM with N words.

Original language	English
Title of host publication	Proceedings - 2022 IEEE International Test Conference, ITC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	489-493
Number of pages	5
ISBN (Electronic)	9781665462709
DOIs	https://doi.org/10.1109/ITC50671.2022.00058
State	Published - 2022
Event	2022 IEEE International Test Conference, ITC 2022 - Anaheim, United States Duration: 23 Sep 2022 → 30 Sep 2022

Publication series

Name	Proceedings - International Test Conference
Volume	2022-September
ISSN (Print)	1089-3539

Conference

Conference	2022 IEEE International Test Conference, ITC 2022
Country/Territory	United States
City	Anaheim
Period	23/09/22 → 30/09/22

Keywords

DFT
March test
STT MRAM
Test

Access to Document

10.1109/ITC50671.2022.00058

應用於運算記憶體之前瞻可靠度及測試框架-總計畫暨子計畫一：應用於運算記憶體之測試技術
Li, J.-F. (PI)
1/08/22 → 31/07/23
Project: Research

Cite this

@inproceedings{16e8ef0913d14378981180f1eef21831,

title = "DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs",

abstract = "Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is one promising nonvolatile memory. In this paper, a design-for-testability (DFT)-enhanced test scheme is proposed to enhance the test quality of STT-MRAMs by adaptively adjusting the read current of the read test operations using a read current-adjustable DFT (RCA-DFT) circuit. A march test, March-MT, is proposed as well. Together with RCA-DFT, March-MT requires 11N test complexity to achieve about 7.26 times of total test quality improvement in comparison with a March-6N test algorithm with fixed read current for a STT-MRAM with N words.",

keywords = "DFT, March test, STT MRAM, Test",

author = "Pan, {Ze Wei} and Li, {Jin Fu}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE International Test Conference, ITC 2022 ; Conference date: 23-09-2022 Through 30-09-2022",

year = "2022",

doi = "10.1109/ITC50671.2022.00058",

language = "???core.languages.en_GB???",

series = "Proceedings - International Test Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "489--493",

booktitle = "Proceedings - 2022 IEEE International Test Conference, ITC 2022",

}

Pan, ZW & Li, JF 2022, DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs. in Proceedings - 2022 IEEE International Test Conference, ITC 2022. Proceedings - International Test Conference, vol. 2022-September, Institute of Electrical and Electronics Engineers Inc., pp. 489-493, 2022 IEEE International Test Conference, ITC 2022, Anaheim, United States, 23/09/22. https://doi.org/10.1109/ITC50671.2022.00058

DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs. / Pan, Ze Wei; Li, Jin Fu.
Proceedings - 2022 IEEE International Test Conference, ITC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 489-493 (Proceedings - International Test Conference; Vol. 2022-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs

AU - Pan, Ze Wei

AU - Li, Jin Fu

PY - 2022

Y1 - 2022

N2 - Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is one promising nonvolatile memory. In this paper, a design-for-testability (DFT)-enhanced test scheme is proposed to enhance the test quality of STT-MRAMs by adaptively adjusting the read current of the read test operations using a read current-adjustable DFT (RCA-DFT) circuit. A march test, March-MT, is proposed as well. Together with RCA-DFT, March-MT requires 11N test complexity to achieve about 7.26 times of total test quality improvement in comparison with a March-6N test algorithm with fixed read current for a STT-MRAM with N words.

AB - Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is one promising nonvolatile memory. In this paper, a design-for-testability (DFT)-enhanced test scheme is proposed to enhance the test quality of STT-MRAMs by adaptively adjusting the read current of the read test operations using a read current-adjustable DFT (RCA-DFT) circuit. A march test, March-MT, is proposed as well. Together with RCA-DFT, March-MT requires 11N test complexity to achieve about 7.26 times of total test quality improvement in comparison with a March-6N test algorithm with fixed read current for a STT-MRAM with N words.

KW - DFT

KW - March test

KW - STT MRAM

KW - Test

UR - http://www.scopus.com/inward/record.url?scp=85146143479&partnerID=8YFLogxK

U2 - 10.1109/ITC50671.2022.00058

DO - 10.1109/ITC50671.2022.00058

M3 - 會議論文篇章

AN - SCOPUS:85146143479

T3 - Proceedings - International Test Conference

SP - 489

EP - 493

BT - Proceedings - 2022 IEEE International Test Conference, ITC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE International Test Conference, ITC 2022

Y2 - 23 September 2022 through 30 September 2022

ER -

DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs

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Keywords

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應用於運算記憶體之前瞻可靠度及測試框架-總計畫暨子計畫一：應用於運算記憶體之測試技術

Cite this