Device linearity improvement of In0.49Ga0.51P/In 0.15Ga0.85As doped-channel FETs with a metal plug alloy process

Feng Tso Chien, Chien Nan Liao, Jin Mu Yin, Hsien Chin Chiu, Yao Tsung Tsai

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The effect of reducing source and drain resistance on the device linearity of doped-channel heterostructure FETs is investigated in this work. The proposed metal plug alloy process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer, which not only enhances the device source resistances, dc, RF and power characteristics, but also improves the device linearity of doped-channel heterostructute FETs. In particular, we compare the performance of dc, RF and microwave power characteristics between proposed partial drain/source ohmic recess metal plug anneal InGaP/InGaAs/GaAs doped-channel FETs (OR-DCFETs) and conventional doped-channel FETs (DCFETs). Due to lower source and drain resistances, OR-DCFETs demonstrate higher device current, higher power-added efficiency (PAE) and especially better device linearity than conventional doped-channel FETs, making OR-DCFETs very suitable for microwave power device applications.

Original languageEnglish
Article number035009
JournalSemiconductor Science and Technology
Issue number3
StatePublished - 1 Mar 2008


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