Designing ultra-low voltage PLL using a bulk-driven technique

Ting Sheng Chao, Yu Lung Lo, Wei Bin Yang, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-μm standard CMOS process with a 0.5V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610MHz with a 0.5V power supply voltage. At 550MHz, the measured rms jitter and peak-to-peak jitter are 8.01ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25mW and the active die area of PLL is 0.04mm2.

Original languageEnglish
Title of host publicationESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference
Pages388-391
Number of pages4
DOIs
StatePublished - 2009
Event35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athens, Greece
Duration: 14 Sep 200918 Sep 2009

Publication series

NameESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Conference

Conference35th European Solid-State Circuits Conference, ESSCIRC 2009
Country/TerritoryGreece
CityAthens
Period14/09/0918/09/09

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