@inproceedings{268dbc0dd06348048bc9854c5153cee2,
title = "Designing ultra-low voltage PLL using a bulk-driven technique",
abstract = "This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-μm standard CMOS process with a 0.5V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610MHz with a 0.5V power supply voltage. At 550MHz, the measured rms jitter and peak-to-peak jitter are 8.01ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25mW and the active die area of PLL is 0.04mm2.",
author = "Chao, {Ting Sheng} and Lo, {Yu Lung} and Yang, {Wei Bin} and Cheng, {Kuo Hsing}",
year = "2009",
doi = "10.1109/ESSCIRC.2009.5325983",
language = "???core.languages.en_GB???",
isbn = "9781424443536",
series = "ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference",
pages = "388--391",
booktitle = "ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference",
note = "35th European Solid-State Circuits Conference, ESSCIRC 2009 ; Conference date: 14-09-2009 Through 18-09-2009",
}