Designing an ultralow-voltage phase-locked loop using a bulk-driven technique

Yu Lung Lo, Wei Bin Yang, Ting Sheng Chao, Kuo Hsing Cheng

Research output: Contribution to journalArticlepeer-review

43 Scopus citations

Abstract

This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-μm standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 mm2.

Original languageEnglish
Pages (from-to)339-343
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume56
Issue number5
DOIs
StatePublished - 2009

Keywords

  • Bulk driven
  • Forward body bias (FBB)
  • Phase-locked loop (PLL)
  • Ultralow voltage
  • Voltage-controlled oscillator (VCO)

Fingerprint

Dive into the research topics of 'Designing an ultralow-voltage phase-locked loop using a bulk-driven technique'. Together they form a unique fingerprint.

Cite this