Design verification by using universal test sets

Beyin Chen; Chung Len Lee; Jwu E. Chen

Design verification by using universal test sets

Beyin Chen
, Chung Len Lee
, Jwu E. Chen

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.

Original language	English
Pages (from-to)	261-266
Number of pages	6
Journal	Proceedings of the Asian Test Symposium
State	Published - 1994
Event	Proceedings of the 3rd Asian Test Symposium - Nara, Jpn Duration: 15 Nov 1994 → 17 Nov 1994

Cite this

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title = "Design verification by using universal test sets",

abstract = "In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.",

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AU - Chen, Beyin

AU - Lee, Chung Len

AU - Chen, Jwu E.

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AB - In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.

UR - https://www.scopus.com/pages/publications/0028713348

M3 - 會議論文

AN - SCOPUS:0028713348

SN - 1081-7735

SP - 261

EP - 266

JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

T2 - Proceedings of the 3rd Asian Test Symposium

Y2 - 15 November 1994 through 17 November 1994

ER -

Design verification by using universal test sets

Abstract

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