Design verification by using universal test sets

Beyin Chen, Chung Len Lee, Jwu E. Chen

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.

Original languageEnglish
Pages (from-to)261-266
Number of pages6
JournalProceedings of the Asian Test Symposium
StatePublished - 1994
EventProceedings of the 3rd Asian Test Symposium - Nara, Jpn
Duration: 15 Nov 199417 Nov 1994

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