Abstract
In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then, theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.
| Original language | English |
|---|---|
| Pages (from-to) | 261-266 |
| Number of pages | 6 |
| Journal | Proceedings of the Asian Test Symposium |
| State | Published - 1994 |
| Event | Proceedings of the 3rd Asian Test Symposium - Nara, Jpn Duration: 15 Nov 1994 → 17 Nov 1994 |