Digital signal processing (DSP) processors for real-time processing of multimedia signals usually include fast reconfigurable parallel adders for the operations of integers with different precisions. This paper presents a reconfigurable carry select adder (CSA). High reconfigurability is achieved with inter-block and infra-block partition schemes. This methodology only causes very small performance penalty and area overhead. Experimental results show that the worst delay of a 64-bit reconfigurable CSA with eight 8-bit blocks is about 2.4ns based on the TSMC 0.18μm technology. Also, the area overhead of the additional partition circuitry is only about 4.6%.
|Number of pages||4|
|State||Published - 2004|
|Event||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
Duration: 6 Dec 2004 → 9 Dec 2004
|Conference||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|Period||6/12/04 → 9/12/04|