Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance

Akancha Gupta, C. K. Chiang, W. Y. Yang, E. R. Hsieh, Steve S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A novel vertical channel face-tunneling field effect transistor (VC-TFET) using Ge/SiGe material is proposed in this paper. The proposed device structure enhances the on-state drive current without increasing the device footprint and also provides lower off-state leakage current, steeper sub-threshold slope and higher Ion/Ioff current ratio compared to the other TFETs. The design of SiGe-material in the drain region suppresses the leakage current, and the channel region with small bandgap Ge enhances the tunneling current. Additionally, the complementary vertical channel TFET is also used to demonstrate the SRAM circuit performance for low power application. Novel SRAM topologies are proposed to eliminate the read disturb and enhance the RSNM/WSNM of SRAM.

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages132-133
Number of pages2
ISBN (Electronic)9781728142326
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Country/TerritoryTaiwan
CityHsinchu
Period10/08/2013/08/20

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