Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification

Yan Chen, Yuan En Yu, Yu Cheng Lin, Chih Hung Hsieh, Muh Tian Shiue, Chih Feng Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we focus on the design of digital baseband inner receiver for Power Line Communication (PLC) system based on IEEE P1901 specification. The baseband receiver is composed of digital received filter, synchronization, fast Fourier transform (FFT), channel estimation/equalization and timing frequency offset (TFO) synchronization. The baseband receiver provides the throughput rate of 170 Mbps with 1024-QAM constellation. The chip is designed with 90 nm CMOS process. The core area is 2.071×2.071 mm2 with the power consumption of 89.9 mW at the supply voltage of 1.0 V.

Original languageEnglish
Title of host publication2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages210-211
Number of pages2
ISBN (Electronic)9781479987443
DOIs
StatePublished - 20 Aug 2015
Event2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 - Taipei, Taiwan
Duration: 6 Jun 20158 Jun 2015

Publication series

Name2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Conference

Conference2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
Country/TerritoryTaiwan
CityTaipei
Period6/06/158/06/15

Keywords

  • Baseband
  • Channel estimation
  • Layout
  • Least squares approximations
  • OFDM
  • Receivers
  • Synchronization

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