Design and VLSI implementation of MPEG audio decoder

Tsung Han Tsai; Thou Ho Chen; Liang Gee Chen

Design and VLSI implementation of MPEG audio decoder

Tsung Han Tsai, Thou Ho Chen, Liang Gee Chen

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

The paper presents a chip design for MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced into half of the original one, and the storage demand too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using the structure silicon compiler in the Genesil system, with 0.8-μm CMOS technology.

Original language	English
Pages	206-210
Number of pages	5
State	Published - 1995
Event	Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 31 May 1995 → 2 Jun 1995

Conference

Conference	Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications
City	Taipei, Taiwan
Period	31/05/95 → 2/06/95

Cite this

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title = "Design and VLSI implementation of MPEG audio decoder",

abstract = "The paper presents a chip design for MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced into half of the original one, and the storage demand too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using the structure silicon compiler in the Genesil system, with 0.8-μm CMOS technology.",

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AU - Chen, Thou Ho

AU - Chen, Liang Gee

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N2 - The paper presents a chip design for MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced into half of the original one, and the storage demand too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using the structure silicon compiler in the Genesil system, with 0.8-μm CMOS technology.

AB - The paper presents a chip design for MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced into half of the original one, and the storage demand too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using the structure silicon compiler in the Genesil system, with 0.8-μm CMOS technology.

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M3 - 會議論文

AN - SCOPUS:0029544418

SP - 206

EP - 210

T2 - Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 31 May 1995 through 2 June 1995

ER -

Design and VLSI implementation of MPEG audio decoder

Abstract

Conference

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