Design and Test of Computing-In Memories

Jin Fu Li

doi:10.1109/ISOCC56007.2022.10031451

Design and Test of Computing-In Memories

Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Computing-in-memory architecture is one good candidate for overcoming the memory-wall bottleneck of von Neumann computing architecture. Many approaches were proposed to modify different types of memories to support the computing function. This paper provides a brief tutorial on computing-in memory (CIM) designs and test techniques. Also, some challenges of CIM design and testing are discussed.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	157-158
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031451
State	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 19 Oct 2022 → 22 Oct 2022

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	19/10/22 → 22/10/22

Keywords

MAC
computing-in memory
test

Access to Document

10.1109/ISOCC56007.2022.10031451

Reconfigurable Deep Neural Network Techniques for Supervised Learning(3/3)
Li, J.-F. (PI)
1/08/21 → 31/07/22
Project: Research
Robustness and Reliability Enhancement Techniques for Deep Neural Network Systems(3/3)
Li, J.-F. (PI)
1/08/21 → 31/07/22
Project: Research

Cite this

@inproceedings{f5da04bbb02f4f6187cef565c5427f2d,

title = "Design and Test of Computing-In Memories",

abstract = "Computing-in-memory architecture is one good candidate for overcoming the memory-wall bottleneck of von Neumann computing architecture. Many approaches were proposed to modify different types of memories to support the computing function. This paper provides a brief tutorial on computing-in memory (CIM) designs and test techniques. Also, some challenges of CIM design and testing are discussed.",

keywords = "MAC, computing-in memory, test",

author = "Li, {Jin Fu}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

year = "2022",

doi = "10.1109/ISOCC56007.2022.10031451",

language = "???core.languages.en_GB???",

series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "157--158",

booktitle = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

}

Li, JF 2022, Design and Test of Computing-In Memories. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 157-158, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 19/10/22. https://doi.org/10.1109/ISOCC56007.2022.10031451

Design and Test of Computing-In Memories. / Li, Jin Fu.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 157-158 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design and Test of Computing-In Memories

AU - Li, Jin Fu

PY - 2022

Y1 - 2022

N2 - Computing-in-memory architecture is one good candidate for overcoming the memory-wall bottleneck of von Neumann computing architecture. Many approaches were proposed to modify different types of memories to support the computing function. This paper provides a brief tutorial on computing-in memory (CIM) designs and test techniques. Also, some challenges of CIM design and testing are discussed.

AB - Computing-in-memory architecture is one good candidate for overcoming the memory-wall bottleneck of von Neumann computing architecture. Many approaches were proposed to modify different types of memories to support the computing function. This paper provides a brief tutorial on computing-in memory (CIM) designs and test techniques. Also, some challenges of CIM design and testing are discussed.

KW - MAC

KW - computing-in memory

KW - test

UR - http://www.scopus.com/inward/record.url?scp=85148430602&partnerID=8YFLogxK

U2 - 10.1109/ISOCC56007.2022.10031451

DO - 10.1109/ISOCC56007.2022.10031451

M3 - 會議論文篇章

AN - SCOPUS:85148430602

T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022

SP - 157

EP - 158

BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th International System-on-Chip Design Conference, ISOCC 2022

Y2 - 19 October 2022 through 22 October 2022

ER -

Design and Test of Computing-In Memories

Abstract

Publication series

Conference

Keywords

Access to Document

Fingerprint

Projects

Reconfigurable Deep Neural Network Techniques for Supervised Learning(3/3)

Robustness and Reliability Enhancement Techniques for Deep Neural Network Systems(3/3)

Cite this