Design and integration for background subtraction and foreground tracking algorithm

Tsung Han Tsai, Chung Yuan Lin, De Zhang Peng, Giua Hua Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Automatic understanding of events happening at a site is the ultimate goal for many visual surveillance systems. Understanding of events requires that certain lower level computer vision tasks be performed. These include foreground detection, labeling foreground parts, and tracking targets. To achieve these tasks, it is necessary to build background subtraction and foreground tracking in the scene. This paper proposed a hardware-oriental algorithm for background subtraction and foreground tracking. To achieve realtime processing and flexibility, the system is then mapped to a SoC architecture with a single camera. The architecture contains two acceleration units and a programmable micro-processor unit. The usage of micro-processor can provide high flexibility for events understanding in different surveillance by user program. And the proposed accelerator hardware unit is used to increase the entire throughput. Simulation results show that the foreground detection and tracking results are satisfied. Performance of the proposed architecture estimated in terms of the number of clocks is brought forward to justify the real-time processing ability for 30 CIF frames per second.

Original languageEnglish
Title of host publication5th International Conference on Information Assurance and Security, IAS 2009
Pages181-184
Number of pages4
DOIs
StatePublished - 2009
Event5th International Conference on Information Assurance and Security, IAS 2009 - Xian, China
Duration: 18 Aug 200920 Sep 2009

Publication series

Name5th International Conference on Information Assurance and Security, IAS 2009
Volume1

Conference

Conference5th International Conference on Information Assurance and Security, IAS 2009
Country/TerritoryChina
CityXian
Period18/08/0920/09/09

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