Design and implementation of DCT/IDCT chip with novel architecture

Kuo Hsing Cheng; Chih Sheng Huang; Chun Pin Lin

doi:10.1109/ISCAS.2000.858858

Design and implementation of DCT/IDCT chip with novel architecture

Kuo Hsing Cheng, Chih Sheng Huang, Chun Pin Lin

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

13 Scopus citations

Abstract

In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operate up to 100 MHz.

Original language	English
Pages (from-to)	IV-741-IV-744
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
DOIs	https://doi.org/10.1109/ISCAS.2000.858858
State	Published - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000

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10.1109/ISCAS.2000.858858

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title = "Design and implementation of DCT/IDCT chip with novel architecture",

abstract = "In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operate up to 100 MHz.",

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T1 - Design and implementation of DCT/IDCT chip with novel architecture

AU - Cheng, Kuo Hsing

AU - Huang, Chih Sheng

AU - Lin, Chun Pin

PY - 2000

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N2 - In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operate up to 100 MHz.

AB - In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operate up to 100 MHz.

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M3 - 會議論文

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VL - 4

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

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Design and implementation of DCT/IDCT chip with novel architecture

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