Design and implementation of DCT/IDCT chip with novel architecture

Kuo Hsing Cheng, Chih Sheng Huang, Chun Pin Lin

Research output: Contribution to journalConference articlepeer-review

13 Scopus citations


In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operate up to 100 MHz.

Original languageEnglish
Pages (from-to)IV-741-IV-744
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2000
EventProceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland
Duration: 28 May 200031 May 2000


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