In this paper, we design an automatic generation environment for hardware accelerator of Fast Fourier Transform (FFT) and inverse Fast Fourier Transform (IFFT) with various parameters. The target application is the FFT/IFFT core from 8 to 8192 points for OFDM systems. With different input parameters and constrains, our FFT/IFFT Soft IP generator can automatically generate a complete design results including the synthesizable Verilog HDL code, test bench, and synthesis scripts files. We also produce the on-chip-bus interface circuit compliant with the AMBA protocol and associated device driver so that the generated IP is ready for system-on-chip (SOC) integration. Therefore, not only reducing the time-to-market development cost, the proposed design can provide a reuse and programmable IP core which is suitable for the SoC applications.
|Number of pages||2|
|Journal||Digest of Technical Papers - IEEE International Conference on Consumer Electronics|
|State||Published - 2005|
|Event||2005 Digest of Technical Papers - International Conference on Consumer Electronics, ICCE 2005 - Las Vegas, NV, United States|
Duration: 8 Jan 2005 → 12 Jan 2005