Design and analysis of a w-band divide-by-three injection-locked frequency divider using second harmonic enhancement technique

Yen Liang Yeh, Hong Yeh Chang

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

Abstract

In this paper, we present design and analysis of a W-band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W-Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than-15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V.

Original languageEnglish
Article number6177292
Pages (from-to)1617-1625
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Volume60
Issue number6 PART 1
DOIs
StatePublished - 2012

Keywords

  • CMOS
  • divide-by-three
  • injection-locked frequency divider (ILFD)
  • phase-locked loop (PLL)

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