Design and analysis of a K-band low-phase-noise phase-locked loop with subharmonically injection-locked technique

Yen Liang Yeh, Hong Yeh Chang

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4 Scopus citations

Abstract

In this paper, we present design and analysis of a K-band (18 to 26.5 GHz) low-phase-noise phase-locked loop (PLL) with the subharmonically injection-locked (SIL) technique. The phase noise of the PLL with subharmonic injection is investigated, and a modified phase noise model of the PLL with SIL technique is proposed. The theoretical calculations agree with the experimental results. Moreover, the phase noise of the PLL can be improved with the subharmonic injection. To achieve K-band operation with low dc power consumption, a divide-by-3 injection-locked frequency divider (ILFD) is used as a frequency prescaler. The measured phase noise of the PLL without injection is -110 dBc/Hz at 1 MHz offset at the operation frequency of 23.08 GHz. With the subharmonic injection, the measured phase noises at 1 MHz offset are -127, -127, and -119 dBc/Hz for the subharmonic injection number NINJ = 2, 3, and 4, respectively. Moreover, the performance of the proposed PLL with and without SIL technique can be compared with the reported advanced CMOS PLLs.

Original languageEnglish
Article number6968688
Pages (from-to)1927-1937
Number of pages11
JournalIEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control
Volume61
Issue number12
DOIs
StatePublished - 1 Dec 2014

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