Crosstalkdriven interconnect optimization by simultaneous gate and wire sizing

Iris Hui Ru Jiang, Yao Wen Chang, Jing Yang Jou

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1MB memory and 19.4min runtime to achieve the precision of within 1 % error on a SUN Spare UltraI workstation.

Original languageEnglish
Pages (from-to)9991010
Number of pages1
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number9
StatePublished - 2000


  • Deep submicrometer
  • Gate sizing
  • Interconnect
  • Performance optimization
  • Physical design
  • Routing


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