Crosstalk-avoidance coding for low-power on-chip bus

Kuang Chin Cheng; Jing Yang Jou

doi:10.1109/ICECS.2008.4675037

Crosstalk-avoidance coding for low-power on-chip bus

Kuang Chin Cheng, Jing Yang Jou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, a crosstalk-avoidance (CA) bus coding approach is developed to produce area-efficient, low-power codes for global data busses. Proposed codes are codes without memory using shielding boundary strategy. Related code generation algorithm is also developed. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2× for heavily coupled busses based on theoretical analysis. As compared to uncoded datawords, proposed codes show 16.1% to 21.5% power-reduction on bus for an equiprobable 32-bit bus design.

Original language	English
Title of host publication	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages	1051-1054
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2008.4675037
State	Published - 2008
Event	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta Duration: 31 Aug 2008 → 3 Sep 2008

Publication series

Name	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/Territory	Malta
City	St. Julian's
Period	31/08/08 → 3/09/08

Access to Document

10.1109/ICECS.2008.4675037

Cite this

Cheng, K. C., & Jou, J. Y. (2008). Crosstalk-avoidance coding for low-power on-chip bus. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp. 1051-1054). Article 4675037 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4675037

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title = "Crosstalk-avoidance coding for low-power on-chip bus",

abstract = "In this paper, a crosstalk-avoidance (CA) bus coding approach is developed to produce area-efficient, low-power codes for global data busses. Proposed codes are codes without memory using shielding boundary strategy. Related code generation algorithm is also developed. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2× for heavily coupled busses based on theoretical analysis. As compared to uncoded datawords, proposed codes show 16.1% to 21.5% power-reduction on bus for an equiprobable 32-bit bus design.",

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Cheng, KC & Jou, JY 2008, Crosstalk-avoidance coding for low-power on-chip bus. in Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4675037, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, pp. 1051-1054, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, Malta, 31/08/08. https://doi.org/10.1109/ICECS.2008.4675037

Crosstalk-avoidance coding for low-power on-chip bus. / Cheng, Kuang Chin; Jou, Jing Yang.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 1051-1054 4675037 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a crosstalk-avoidance (CA) bus coding approach is developed to produce area-efficient, low-power codes for global data busses. Proposed codes are codes without memory using shielding boundary strategy. Related code generation algorithm is also developed. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2× for heavily coupled busses based on theoretical analysis. As compared to uncoded datawords, proposed codes show 16.1% to 21.5% power-reduction on bus for an equiprobable 32-bit bus design.

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Crosstalk-avoidance coding for low-power on-chip bus

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