Cost-efficient built-In redundancy analysis with optimal repair rate for RAMs

Ting Ju Chen, Jin Fu Li, Tsu Wei Tseng

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Built-in self-repair (BISR) techniques are widely used for the repair of embedded memories. One of the key components of a BISR circuit is the built-in redundancy-analysis (BIRA) module, which allocates redundancies according to the designed redundancy analysis algorithm. Thus, the BIRA module affects the repair rate of the BISR circuit. Existing BIRA schemes for RAMs can provide the optimal repair rate (the ratio of the number of repaired RAMs to the number of defective RAMs), but they require either high area cost or multiple test runs. This paper proposes a BIRA scheme for RAMs, which can provide the optimal repair rate using very low area cost and single test run. Furthermore, the BIRA is designed as reconfigurable such that it can be shared by multiple RAMs. Experimental results show that the area cost for implementing the proposed BIRA scheme is much lower than that of existing BIRA schemes with optimal repair rate. A test chip is also implemented to demonstrate the proposed BIRA scheme.

Original languageEnglish
Article number6200438
Pages (from-to)930-940
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume31
Issue number6
DOIs
StatePublished - 2012

Keywords

  • Built-in redundancy analysis (BIRA)
  • built-in self-repair (BISR)
  • built-in self-test
  • local bitmap
  • RAMs
  • redundancy

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