Cost-effective TAP-controlled serialized compressed scan architecture for 3D stacked ICs

Chen An Chen; Yee Wen Chen; Chun Lung Hsu; Ming Hsueh Wu; Kun Lun Luo; Bing Chuan Bai; Liang Chia Cheng

doi:10.1109/ATS.2013.29

Cost-effective TAP-controlled serialized compressed scan architecture for 3D stacked ICs

Chen An Chen, Yee Wen Chen, Chun Lung Hsu, Ming Hsueh Wu, Kun Lun Luo, Bing Chuan Bai, Liang Chia Cheng

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.

Original language	English
Article number	6690625
Pages (from-to)	107-108
Number of pages	2
Journal	Proceedings of the Asian Test Symposium
DOIs	https://doi.org/10.1109/ATS.2013.29
State	Published - 2013
Event	2013 22nd Asian Test Symposium, ATS 2013 - Yilan, Taiwan Duration: 18 Nov 2013 → 21 Nov 2013

Keywords

3D-SIC
SCSA
SCSG

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10.1109/ATS.2013.29

Cite this

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title = "Cost-effective TAP-controlled serialized compressed scan architecture for 3D stacked ICs",

abstract = "This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.",

keywords = "3D-SIC, SCSA, SCSG",

author = "Chen, {Chen An} and Chen, {Yee Wen} and Hsu, {Chun Lung} and Wu, {Ming Hsueh} and Luo, {Kun Lun} and Bai, {Bing Chuan} and Cheng, {Liang Chia}",

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AU - Chen, Chen An

AU - Chen, Yee Wen

AU - Hsu, Chun Lung

AU - Wu, Ming Hsueh

AU - Luo, Kun Lun

AU - Bai, Bing Chuan

AU - Cheng, Liang Chia

PY - 2013

Y1 - 2013

N2 - This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.

AB - This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.

KW - 3D-SIC

KW - SCSA

KW - SCSG

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M3 - 會議論文

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SP - 107

EP - 108

JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

M1 - 6690625

T2 - 2013 22nd Asian Test Symposium, ATS 2013

Y2 - 18 November 2013 through 21 November 2013

ER -

Cost-effective TAP-controlled serialized compressed scan architecture for 3D stacked ICs

Abstract

Keywords

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