Core-based system-on-chip testing: Challenges and opportunities

C. W. Wu, J. F. Li, C. T. Huang

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

With the advent of deep-submicron technologies, system-on-chip (SOC) designs, consisting of reusable cores from multiple sources is becoming feasible and popular. However, the complexity of SOC testing is much higher than that of testing conventional VLSI chips. SOC testing involves applying test patterns to and analyzing the corresponding response from each and every core. In addition, the user-defined logic, as well as the final integrated chip, has to be tested. There are new challenges and issues, such as core isolation, test access, test pattern translation (from core to chip), test integration and scheduling, test automation, etc. Furthermore, to make SOC and core test plug-and-play, a standard is being proposed-the IEEE P1500 standard. This paper discusses in detail the challenges and issues in core-based SOC testing. We also describe some existing solutions used to tackle these problems, including the IEEE P1500 that is an attempt to standardize the test interface (called the Test Wrapper) between a core and its SOC host and the Core Test Language (CTL) for test automation. Opportunities for research topics and tools for test automation are also discussed.

Original languageEnglish
Pages (from-to)335-353
Number of pages19
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Volume8
Issue number4
StatePublished - Nov 2001

Keywords

  • Built-in-self-test (BIST)
  • Core test language
  • IC testing
  • IEEE P1500 standard
  • System-on-chip (SOC)
  • Test scheduling

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