Configurable 8T SRAM for Enbling in-Memory Computing

Han Chun Chen, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8 $T$ SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18μm CMOS technology.

Original languageEnglish
Title of host publication2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages112-116
Number of pages5
ISBN (Electronic)9781728114392
DOIs
StatePublished - Apr 2019
Event2nd International Conference on Communication Engineering and Technology, ICCET 2019 - Nagoya, Japan
Duration: 12 Apr 201915 Apr 2019

Publication series

Name2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019

Conference

Conference2nd International Conference on Communication Engineering and Technology, ICCET 2019
Country/TerritoryJapan
CityNagoya
Period12/04/1915/04/19

Keywords

  • computing architecture
  • content addressable memory
  • static random access memory

Fingerprint

Dive into the research topics of 'Configurable 8T SRAM for Enbling in-Memory Computing'. Together they form a unique fingerprint.

Cite this