Configurable 8T SRAM for Enbling in-Memory Computing

Han Chun Chen; Jin Fu Li; Chun Lung Hsu; Chi Tien Sun

doi:10.1109/ICCET.2019.8726871

Configurable 8T SRAM for Enbling in-Memory Computing

Han Chun Chen, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8 $T$ SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18μm CMOS technology.

Original language	English
Title of host publication	2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	112-116
Number of pages	5
ISBN (Electronic)	9781728114392
DOIs	https://doi.org/10.1109/ICCET.2019.8726871
State	Published - Apr 2019
Event	2nd International Conference on Communication Engineering and Technology, ICCET 2019 - Nagoya, Japan Duration: 12 Apr 2019 → 15 Apr 2019

Publication series

Name	2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019

Conference

Conference	2nd International Conference on Communication Engineering and Technology, ICCET 2019
Country/Territory	Japan
City	Nagoya
Period	12/04/19 → 15/04/19

Keywords

computing architecture
content addressable memory
static random access memory

Access to Document

10.1109/ICCET.2019.8726871

Cite this

Chen, H. C., Li, J. F., Hsu, C. L., & Sun, C. T. (2019). Configurable 8T SRAM for Enbling in-Memory Computing. In 2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019 (pp. 112-116). Article 8726871 (2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCET.2019.8726871

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abstract = "To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8 $T$ SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18μm CMOS technology.",

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author = "Chen, {Han Chun} and Li, {Jin Fu} and Hsu, {Chun Lung} and Sun, {Chi Tien}",

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Chen, HC, Li, JF , Hsu, CL & Sun, CT 2019, Configurable 8T SRAM for Enbling in-Memory Computing. in 2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019., 8726871, 2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019, Institute of Electrical and Electronics Engineers Inc., pp. 112-116, 2nd International Conference on Communication Engineering and Technology, ICCET 2019, Nagoya, Japan, 12/04/19. https://doi.org/10.1109/ICCET.2019.8726871

Configurable 8T SRAM for Enbling in-Memory Computing. / Chen, Han Chun; Li, Jin Fu ; Hsu, Chun Lung et al.
2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 112-116 8726871 (2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8 $T$ SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18μm CMOS technology.

AB - To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8 $T$ SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18μm CMOS technology.

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KW - static random access memory

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PB - Institute of Electrical and Electronics Engineers Inc.

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Chen HC, Li JF , Hsu CL, Sun CT. Configurable 8T SRAM for Enbling in-Memory Computing. In 2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 112-116. 8726871. (2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019). doi: 10.1109/ICCET.2019.8726871

Configurable 8T SRAM for Enbling in-Memory Computing

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