Compiled-code parallel pattern logic simulator with inertial delay model

Kuo Chan Huang, Chung Len Lee, Jwu E. Chen

Research output: Contribution to journalConference articlepeer-review


This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating with inertial functions, to execute event-canceling operation for gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it surpasses significantly over the conventional time wheel event-driven simulator in the simulation speed. In addition, it is also found that, significant percentage (27%) of hazards should be eliminated when only the transport delay is considered in the simulation.

Original languageEnglish
Pages (from-to)1716-1719
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1997
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: 9 Jun 199712 Jun 1997


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