Abstract
Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problems. Recently, the Random Access Scan (RAS) scheme offers a solution to alleviate the above problems. In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a segmented random scan test with a few seed patterns to test the DUT and, secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, Test Response Abundant, Constrained Static Compaction, and Bit Propagation Before Test Vector Dropping, it is very effective in reducing bit flipping and test data volume and consequently test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.
Original language | English |
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Pages (from-to) | 229-239 |
Number of pages | 11 |
Journal | International Journal of Electrical Engineering |
Volume | 13 |
Issue number | 3 |
State | Published - Aug 2006 |
Keywords
- DFT
- Low power test
- Random-access-scan
- Test compression