TY - JOUR
T1 - Case study of failure analysis and guardband determination for a 64 M-bit DRAM
AU - Kao, Chin Te
AU - Wu, Sam
AU - Chen, Jwu E.
PY - 2000
Y1 - 2000
N2 - The chips with defects, which escape the test, will cause the quality problem and will hurt the goodwill and decline the revenue. It is important to look for the defect root causes and to derive the prevention strategy. In this paper, a case study of a 64 M-DRAM is used to demonstrate the approaches of failure analysis in silicon debug stage and, consequently, the determination of the tests for the production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low-test cost. The root causing, electrical modeling of defects, test selection and guardband determination will be introduced. Finally, a quantitative measure is given to show the value of failure analysis for a high volume DRAM product.
AB - The chips with defects, which escape the test, will cause the quality problem and will hurt the goodwill and decline the revenue. It is important to look for the defect root causes and to derive the prevention strategy. In this paper, a case study of a 64 M-DRAM is used to demonstrate the approaches of failure analysis in silicon debug stage and, consequently, the determination of the tests for the production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low-test cost. The root causing, electrical modeling of defects, test selection and guardband determination will be introduced. Finally, a quantitative measure is given to show the value of failure analysis for a high volume DRAM product.
UR - http://www.scopus.com/inward/record.url?scp=0034505823&partnerID=8YFLogxK
M3 - 會議論文
AN - SCOPUS:0034505823
SN - 1081-7735
SP - 447
EP - 451
JO - Proceedings of the Asian Test Symposium
JF - Proceedings of the Asian Test Symposium
T2 - 9th Asian Test Symposium
Y2 - 4 December 2000 through 6 December 2000
ER -