Built-in self-test for phase-locked loops

Chun Lung Hsu, Yiting Lai, Shu Wei Wang

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

Abstract

An effective built-in self-test (BIST) structure of a phase-locked loop (PLL) in digital applications is presented in this paper. The proposed BIST structure can identify possible faults in any block such as the phase detector, charge pump, loop filter, voltage-controlled oscillator and divide-by-N of the PLL. The key advantage of this approach is that it uses all existing blocks in PLL for measuring and testing, reducing the chip area overhead. Restated, the proposed approach does not alter any existing analog circuits. Rather, the proposed approach only adds some small circuits to the PLL and requires a slight modification of the digital part. The final test outputs are digital values which can increase the reliability of the proposed BIST structure. Physical chip design and fault simulation results indicate the characteristics of the proposed BIST structure, namely, high fault coverage (97.2 %) and low area overhead (2.78%).

Original languageEnglish
Pages (from-to)996-1002
Number of pages7
JournalIEEE Transactions on Instrumentation and Measurement
Volume54
Issue number3
DOIs
StatePublished - Jun 2005

Keywords

  • Area overhead
  • Built-in self-test (BIST)
  • Fault coverage
  • Phase-locked loop (PLL)
  • Testing

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