Built-in self-diagnosis and test time reduction techniques for NAND flash memories

Che Wei Chou, Chih Sheng Hou, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents a low-cost built-in self-diagnosis (BISD) scheme for NAND flash memories, which can support the March-like test algorithms with page-oriented data backgrounds. Two simple test time reduction techniques are also proposed to reduce the test time. Experimental results show that the proposed BISD circuit for a 2M-bit flash memory only needs 1.7K gates. Also, the proposed test time reduction techniques can effectively reduce the test time. Analysis results show that they can reduce the test time to 48.628% of the normal test scheme for a 4G-bit flash memory tested by the March-FT test algorithm with solid data backgrounds.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages260-263
Number of pages4
DOIs
StatePublished - 2011
Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
Duration: 25 Apr 201128 Apr 2011

Publication series

NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country/TerritoryTaiwan
CityHsinchu
Period25/04/1128/04/11

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