BIST for clock jitter measurements

Kuo Hsing Cheng, Shu Yu Jiang, Zong Shen Chen

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

For high-speed circuit testing, traditional ways are not enough in measuring the clock jitter. In these traditional ways, the external equipment is used to measure the analog clock signal. It would distort the tested clock signal and change the measure result. In order to achieve a more convenient clock jitter measurement, a Time to Digital Converter (TDC) technique is used to output an all-digital data in the proposed method. And, a Built-In-Self-Test (BIST) method is used to realize the proposed method. However, even if some usable BIST methods have been proposed, the requirements of the test time and circuit area still limited the circuit application. In order to release this requirement, a new BIST method is proposed. A continuous clock jitter measurement method is adopted to make a real-time measurement. And, with the proposed pre-delayed sample clock, no more extra delay cells are needed. The circuit area and test time can be significantly reduced. Furthermore, with an improved circuit structure, the circuit stability also can be increased and no more external jitter-free clock is needed to sample the clock jitter.

Original languageEnglish
Pages (from-to)V577-V580
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
StatePublished - 2003
EventProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003

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