BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

Yun Chao Yu; Chi Chun Yang; Jin Fu Li; Chih Yen Lo; Chao Hsun Chen; Jenn Shiang Lai; Ding Ming Kwai; Yung Fa Chou; Cheng Wen Wu

doi:10.1109/ATS.2014.13

BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

Yun Chao Yu, Chi Chun Yang, Jin Fu Li, Chih Yen Lo, Chao Hsun Chen, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 - 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.

Original language	English
Title of host publication	Proceedings - 23rd Asian Test Symposium, ATS 2014
Publisher	IEEE Computer Society
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781479960309
DOIs	https://doi.org/10.1109/ATS.2014.13
State	Published - 7 Dec 2014
Event	23rd Asian Test Symposium, ATS 2014 - Hangzhou, China Duration: 16 Nov 2014 → 19 Nov 2014

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Conference

Conference	23rd Asian Test Symposium, ATS 2014
Country/Territory	China
City	Hangzhou
Period	16/11/14 → 19/11/14

Keywords

3D IC
BIST
DRAM
at-speed test
low power
through silicon via

Access to Document

10.1109/ATS.2014.13

Cite this

Yu, Y. C., Yang, C. C., Li, J. F., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., Chou, Y. F., & Wu, C. W. (2014). BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs. In Proceedings - 23rd Asian Test Symposium, ATS 2014 (pp. 1-6). Article 06979068 (Proceedings of the Asian Test Symposium). IEEE Computer Society. https://doi.org/10.1109/ATS.2014.13

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title = "BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs",

abstract = "Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 - 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.",

keywords = "3D IC, BIST, DRAM, at-speed test, low power, through silicon via",

author = "Yu, {Yun Chao} and Yang, {Chi Chun} and Li, {Jin Fu} and Lo, {Chih Yen} and Chen, {Chao Hsun} and Lai, {Jenn Shiang} and Kwai, {Ding Ming} and Chou, {Yung Fa} and Wu, {Cheng Wen}",

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doi = "10.1109/ATS.2014.13",

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Yu, YC, Yang, CC, Li, JF, Lo, CY, Chen, CH, Lai, JS, Kwai, DM, Chou, YF & Wu, CW 2014, BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs. in Proceedings - 23rd Asian Test Symposium, ATS 2014., 06979068, Proceedings of the Asian Test Symposium, IEEE Computer Society, pp. 1-6, 23rd Asian Test Symposium, ATS 2014, Hangzhou, China, 16/11/14. https://doi.org/10.1109/ATS.2014.13

BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs. / Yu, Yun Chao; Yang, Chi Chun; Li, Jin Fu et al.
Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, 2014. p. 1-6 06979068 (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 - 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.

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ER -

BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

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