BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

Yun Chao Yu, Chi Chun Yang, Jin Fu Li, Chih Yen Lo, Chao Hsun Chen, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 - 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.

Original languageEnglish
Title of host publicationProceedings - 23rd Asian Test Symposium, ATS 2014
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781479960309
StatePublished - 7 Dec 2014
Event23rd Asian Test Symposium, ATS 2014 - Hangzhou, China
Duration: 16 Nov 201419 Nov 2014

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference23rd Asian Test Symposium, ATS 2014


  • 3D IC
  • at-speed test
  • BIST
  • DRAM
  • low power
  • through silicon via


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