BECOME: Behavior level circuit synthesis based on structure mapping.

Ruey Sing Wei, Steven Rothweiler, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

The BECOME system for behavior-level circuit synthesis is presented. BECOME accepts circuit models written in C-like behavior level modeling languages and synthesizes them into different technologies such as PLA, PLD, and standard cells. The system assumes a finite-state-machine circuit model with an external view of only primary inputs and outputs. A minimal set of registers/latches are created automatically when necessary as implied by the behavioral model. A front end extracts the circuit's Boolean behavior from the behavioral model using an approach called structure mapping. Logic minimization subsystems then minimize this Boolean description according to the chosen implementation technology. BECOME extracts and utilizes behavioral don't-cares and supports multiple assignments, symbolic states, parallel (nonprocedural) constructs, and macro facilities using predesigned logic libraries. Experimental data of models from two modeling languages are presented.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages409-414
Number of pages6
ISBN (Print)0818688645
StatePublished - 1988

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

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