Bandwidth balancing scheme for shared buffer memory switch

Jung Shyr Wu, Cheng Chang Ke

Research output: Contribution to journalArticlepeer-review


Researchers have proposed many memory switching architectures for the ATM. Of various architectures, the shared buffer memory switch (SBMS) seems to have the highest hardware-utilization efficiency. It can also be modified to perform multicasting functions for providing conference services and distribution services. However, multicast cells always own higher priority to be served in original Hitachi-type SBMS architecture such that unicast cells must endure longer delay time. We propose a bandwidth balancing scheme to overcome this unfair phenomenon. However, the implementation is simple and cost effective. Performance results are also provided to verify its effectiveness.

Original languageEnglish
Pages (from-to)147-152
Number of pages6
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Issue number2
StatePublished - May 1995


Dive into the research topics of 'Bandwidth balancing scheme for shared buffer memory switch'. Together they form a unique fingerprint.

Cite this