Bandwidth balancing scheme for shared buffer memory switch

Researchers have proposed many memory switching architectures for the ATM. Of various architectures, the shared buffer memory switch (SBMS) seems to have the highest hardware-utilization efficiency. It can also be modified to perform multicasting functions for providing conference services and distribution services. However, multicast cells always own higher priority to be served in original Hitachi-type SBMS architecture such that unicast cells must endure longer delay time. We propose a bandwidth balancing scheme to overcome this unfair phenomenon. However, the implementation is simple and cost effective. Performance results are also provided to verify its effectiveness.