Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost

Tsu Wei Tseng, Chih Sheng Hou, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Built-in self-repair (BISR) techniques are widely used to enhance the yield of memories in a system-on-chip (SOC). A SOC typically consists of hundreds of memories. Cost-efficient BISR schemes for repairing those memories thus are imperative. In this paper, we propose a memory BISR automatic generation (MBAG) framework for designing memory BISR circuits in a SOC. The MBAG framework consists of a test scheduling engine and a memory grouping engine for the minimization of test time and area cost of the BISR circuits. The test scheduling algorithm has been presented in our previous work [1]. In this paper, therefore, we focus on the introduction of the grouping algorithm determining the memories which can share a BISR circuit under the constraints of distance and scheduling results. Simulation results show that the proposed MBAG can generate reconfigurable BISR circuits for 20 memories such that 50% area reduction is achieved in comparison with a dedicated BISR scheme if the distance constraint is 3mm and the test power constraint is 80mW.

Original languageEnglish
Title of host publicationProceedings - 28th IEEE VLSI Test Symposium, VTS10
Pages21-26
Number of pages6
DOIs
StatePublished - 2010
Event28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States
Duration: 19 Apr 201022 Apr 2010

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference28th IEEE VLSI Test Symposium, VTS10
Country/TerritoryUnited States
CitySanta Cruz, CA
Period19/04/1022/04/10

Fingerprint

Dive into the research topics of 'Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost'. Together they form a unique fingerprint.

Cite this