Automatic gain control VLSI architecture for ADSL-1 cap system

Ch K. Wang, Ch M. Lin, M. T. Shiue

Research output: Contribution to journalArticlepeer-review


A mixed analog-digital AGC (Automatic Gain Control) VLSI architecture is proposed for CAP-based (Carrierless Amplitude/Phase Modulation) ADSL-1 (Asymmetric Digital Subscriber Line) digital communication system. The AGC is composed of a VGA (Variable-Gain-Amplifier), a BPF (Band-Pass Filter) and a gain-and-buffer as the signal forward path. The feedback path, which is composed of an autocorrelation function, a block for peak detection, a DAC, an integrator and an attenuator, detects the peak value of the autocorrelation of the training sequence. This architecture shares the digital circuit that is originally used to detect the channel delay for training the equalizer. A Barker code of 5 (3, 3, 3, -3, 3) is chosen for both training the AGC and detecting the channel delay. Both C-language and HSPICE2 simulations show that the convergent time of the AGC for ADSL-1 loops (1 kft ≈ 18 kft) is 300 μs ≈ 600 μs.

Original languageEnglish
Pages (from-to)261-268
Number of pages8
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Issue number3
StatePublished - Aug 1996


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